Members

• Nicolò Speciale
  
• Luca De Marchi
• Emanuele Baravelli

Project description

FinFET is widely recognized as one of the favorite candidates to replace bulk planar transistors thanks to (i) an improved SCE control due to structural confinement, (ii) a reduced sensitivity to random dopant fluctuations (RD) because of the low channel doping, and (iii) the possibility of being co-integrated with conventional CMOS technology. On the other hand, due to continued scaling, roughness in printed transistor features is no more negligible when compared with the device critical dimension (CD).

Our research activity includes a detailed investigation of the impact of line-edge roughness (LER) on FinFET electrical variability and the stability of FinFET-based SRAM circuits. An automated Matlab-TCAD flow has been implemented, which allows generating large ensembles of 2D and 3D device structures affected by roughness with proper statisrical features. Physical and mixed-mode simulations are then carried on and resulting distributions of electrical performance are statistically characterized.

Several process options have been compared with this approach, including resist-defined and spacer-defined fin patterning as well as different doping profiles. The impact of LER on SRAMs has been investigated taking into account cell sizing, crystal orientation and gate stack. As a result, relative importance of different contributions to device and circuit mismatch has been assessed for the LSTP-32nm node, providing useful guidelines for process and device designers.

Contact: Emanuele Baravelli >  This e-mail address is being protected from spam bots, you need JavaScript enabled to view it

Collaborations

• IMEC, Belgium

References